Rare project developers

[Alexander Gall <>]

Just (re-)discovered this from an answer by Vladimir in the forum:

bfrt.tf2.device_configuration> dump
-----------------------------> dump()
----- device_configuration Dump Start -----
Default Entry:
Entry data:
    num_pipes                      : 0x00000004
    num_max_ports                  : 0x00000104
    num_front_ports                : 0x00000104
    pcie_cpu_port                  : 0x00000000
    eth_cpu_port_list              : [2, 3, 4, 5]
    internal_port_list             : []
    external_port_list             : [136, 137, 138, 139, 140, 141, 142, 143, 
144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 
159, 160, 161, 162, 163, 164, 165, 16 6, 167, 168, 169, 170, 171, 172, 173, 
174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 
189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 320, 321, 322, 323, 32 
4, 325, 326, 327, 312, 313, 314, 315, 316, 317, 318, 319, 304, 305, 306, 307, 
308, 309, 310, 311, 296, 297, 298, 299, 300, 301, 302, 303, 288, 289, 290, 
291, 292, 293, 294, 295, 280, 281, 28 2, 283, 284, 285, 286, 287, 272, 273, 
274, 275, 276, 277, 278, 279, 264, 265, 266, 267, 268, 269, 270, 271, 400, 
401, 402, 403, 404, 405, 406, 407, 392, 393, 394, 395, 396, 397, 398, 399, 41 
6, 417, 418, 419, 420, 421, 422, 423, 408, 409, 410, 411, 412, 413, 414, 415, 
432, 433, 434, 435, 436, 437, 438, 439, 424, 425, 426, 427, 428, 429, 430, 
431, 448, 449, 450, 451, 452, 453, 45 4, 455, 440, 441, 442, 443, 444, 445, 
446, 447, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 40, 
41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 24, 25, 26, 27 , 
28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 8, 9, 10, 11, 12, 13, 14, 15, 
16, 17, 18, 19, 20, 21, 22, 23]
    recirc_port_list               : [1, 6, 7, 128, 129, 130, 131, 132, 133, 
134, 135, 256, 257, 258, 259, 260, 261, 262, 263, 384, 385, 386, 387, 388, 
389, 390, 391]
    intr_based_link_monitoring     : False
    flow_learn_intr_mode           : False
    lrt_dr_timeout_msec            : 0x00000032
    flow_learn_timeout_usec        : 0x000001F4

----- device_configuration Dump End -----

On Tofino2, all "special" ports are ports 0-7 on each pipe. Vladimir
doesn't say it explicitly, but I guess that port #0 (on logical pipe
#0) is always the CPU PCIe port. All of these ports seem to be for
recirculation on all other pipes. The secret will only be revealed in
the Intel Academy for Tofino2 :)

-- 
Alex

On Fri, 3 Jun 2022 10:13:48 +0200, Alexander Gall <> said:

> On Fri, 3 Jun 2022 09:50:49 +0200, Frédéric LOUI <> 
> said:
>> Hi Alex,
bf-sde> cfg
>> DVM:: Board configuration:
>> +----+------+-----+---+--------------------------------
>> |dev | port                                            
>> +----+------+-----+---+--------------------------------
>> |  0 |  68   
>> |  0 | 128   
>> |  0 | 192   
>> |  0 | 196   
>> +----+------+-----+---+-------------------------------- 

>> You should be able to use the same command for TOIFNO 2 in order to find 
>> teh CPU port (and recirculation port)

>> I should be curious able the output :)

> Hm:

f-sde> cfg
> DVM:: Board configuration:
> +----+------+-----+---+--------------------------------
> |dev | port
> +----+------+-----+---+--------------------------------
> |  0 |   0
> |  0 |   1
> |  0 |   6
> |  0 | 128
> |  0 | 130
> |  0 | 132
> |  0 | 134
> |  0 | 168
> |  0 | 256
> |  0 | 258
> |  0 | 260
> |  0 | 262
> |  0 | 384
> |  0 | 386
> |  0 | 388
> |  0 | 390

> Relative ports per pipe:

> Pipe0: 0,1,6
> Pipe1: 0,2,4,6,40
> Pipe2: 0,2,4,6
> Pipe3: 0,2,4,6

> I can't really identify them. My guess would be that 168 is the CPU
> PCIe port. Somehow I remember that there is a specific command to
> display just the CPU port, but I just can't find it any more.

> -- 
> Alex
-- 
Alexander Gall, Network

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