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Re: [rare-dev] RARE@400G


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  • From: mc36 <>
  • To: Alexander Gall <>, "" <>
  • Subject: Re: [rare-dev] RARE@400G
  • Date: Fri, 3 Jun 2022 11:53:09 +0200

congrats!!! :)

On 6/3/22 11:06, Alexander Gall wrote:

Folks,

I just performed the first successful ping between RARE running on the
AS9516_32D and a Cisco 8201 via a 400G port :)

The last hurdle was to find out which port on the Tofino2 chip
represents the CPU PCIe port that provides the communication to the
control plane. Lacking documentation I had to do this by trial and
error. Luckily, the first try was a success: it's device port #0 (but
maybe Tofino2 has more than one, I don't know).

Most of the code is already in the various Git repos, but not all of
it. I'll try to do this later today or next week.




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