Rare project developers

[Alexander Gall <>]

On Fri, 3 Jun 2022 07:56:26 +0200, mc36 <> said:

> hi,
> On 6/3/22 07:46, Alexander Gall wrote:
>> On Thu, 2 Jun 2022 19:44:45 +0200, mc36 <> said:
>> 
>>> hi,
>>> finally nothing worked but a very similar approach what you did as 
>>> workaround:
>>> https://bitbucket.software.geant.org/projects/RARE/repos/rare/commits/d33cd1def306bb2e88a641dbd7b343f748c4ce01
>>> the sap_en/decap is not ternary anymore... for now, i just compiled some 
>>> of the tester vms...
>>> could you please give it a spin? but in the long run, imho i'll need to 
>>> replicate the whole
>>> stuff i'm doing for tofino1 for tofino2 if we're willing to support the 
>>> new chip...
>> 
>> Everything compiles for Tofino1 and 2 :) I'm going to add support for
>> the AS9516-32D now. That alone will not be sufficient. We'll have to
> sounds cool, thanks!

>> at least adapt the forwarder too, at least for the new supported
>> interface speeds.  But let's take one step at a time :)
>> 
> moreover tofino2 as far as i know have 4 more stages so that will need a 
> completely
> different optimization round to take advantage of these additional 
> resources...

Actually it's 8 more stages (20 per pipe) on that particular platform
(with the BFN-T20-128Q chip). There are finally some Tofino2 documents
available on the Intel site :)

-- 
Alex