Rare project developers

[Frédéric LOUI <>]

+ adding rare-users and rare-dev as the answer might be of interest for the 
others

> could you please send us the link/post you mentioned to configure the SDE 
> VM? 
https://wiki.geant.org/pages/viewpage.action?pageId=148084243

This is a bit outdated, but this will give you a rough idea about how to 
start RARE/freeRtr and bf_switch

> For the hardware machine running the VM, could you please repeat the 
> parameters you would suggest?
> Besides the 64G RAM, what would you recommend for CPU, HDD, OS, ...? 
1- 4 vCPU
2- 8G bare minimum but 16G should be fine. If you have plenty of RAM and plan 
to mutualise this VM with multiple students 32G/64G is good.
3- 50G of storage is sufficient. I’m not sure but SDE full installation with 
p4studio, If I’m not mistaken can takes 8G.
    If you plan to have any single SDE version installed, please consider to 
more storage. 
    Maybe, Alex’s SDE-shell will take less as everything will comes from a 
binary cache.

4- If you are using Nixpkg RARE/freeRtr build, any linux should be OK. But we 
mostly tested with Debian stable.
    Therefore I would just recommend Debian stable :)
  
> p.s. I was also wondering whether I could share the RARE/freeRtr 
> information with a group at University of Oxford? 

You can certainly share all RARE/freeRtr information with anyone. (Apart 
everything related to NDA)

>  I was formerly a visitor to this group led by Prof. Noa Zilberman, and 
> they are also working a lot on P4 research and education with Intel Tofino.
> Perhaps it will help RARE spread its influence? 

Sure, it is really up to you. I recommend to subscribe to rare-users and 
rare-dev mailing list.

> In the event that I am allowed to share the information, which link/repo 
> would you recommend I share?

All of our material/work is public.
rare.freertr.org
blog.freertr.org
docs.freertr.org

And obviously Csaba’s freeRtr home page.
www.freertr.org

There is also a RARE/freeRtr Discord server, IRC #freertr @ Hackint and 
Twitter (https://twitter.com/rare_freerouter)


Last bit not least, please consider start your development with Alex’s 
excellent SDE-shell here.
(Assuming that you have all NDA related matters taken care of, it should make 
gain a lot of time)

https://github.com/alexandergall/bf-sde-nixpkgs

Alex’s jewel basically let you transform any Linux into a INTEL TOFINO dev 
environment
 whether with ASIC such as Wedge 100BF 32X or virtual model as you have 
learnt during INTEL training class. (Which I recommend for your students)
He is is trying to have SDE Nixpkg up to date by following tightly INTEL SDE 
release (as of now SDE 9.12.x)

I’m using it personally as a dev environment and just even forget how to 
install SDE with p4studio ( ~ 45 minutes … :-) )
Assuming you have Nixpkg already installed, Installing SDE with his package 
is really easy (almost one line, or maybe or two ...)

But, pay attention that you must have signed NDA with INTEL and also provide 
SDE tarball.

> Le 17 févr. 2023 à 11:43, Mingyuan Zang <> a écrit :
> 
> Hi Frederic,
> 
> Thank you so much for today's sync meeting! Based on our discussion, could 
> you please send us the link/post you mentioned to configure the SDE VM? 
> 
> For the hardware machine running the VM, could you please repeat the 
> parameters you would suggest? Besides the 64G RAM, what would you recommend 
> for CPU, HDD, OS, ...? 
> 
> p.s. I was also wondering whether I could share the RARE/freeRtr 
> information with a group at University of Oxford? I was formerly a visitor 
> to this group led by Prof. Noa Zilberman, and they are also working a lot 
> on P4 research and education with Intel Tofino. Perhaps it will help RARE 
> spread its influence? 
> 
> In the event that I am allowed to share the information, which link/repo 
> would you recommend I share?
> 
> Many thanks!
> 
> 
> Best Regards,
> Ming
> 
> 
> -----Original Message-----
> From: Frédéric LOUI <> 
> Sent: 15. februar 2023 18:11
> To: Mingyuan Zang <>
> Cc: Henrik Wessing <>
> Subject: Re: RARE CPE code compilation on Tofino
> 
> Sure !
> 
>> Le 15 févr. 2023 à 17:28, Mingyuan Zang <> a écrit :
>> 
>> Can we meet at 9.30-10am? 30min might be enough for sync? Many thanks! 
>> 
>> Best Regards,
>> Ming
>> 
>> 
>> -----Original Message-----
>> From: Frédéric LOUI <> 
>> Sent: 15. februar 2023 17:24
>> To: Mingyuan Zang <>
>> Cc: Henrik Wessing <>
>> Subject: Re: RARE CPE code compilation on Tofino
>> 
>> I’m available from 9h->10h AM before our call.
>> 
>> Or Friday afternoon … (I have unfortunately  a VC after our call :-( )
>> 
>>> Le 15 févr. 2023 à 17:19, Mingyuan Zang <> a écrit :
>>> 
>>> Hi Frederic,
>>> 
>>> Thank you so much for your prompt and detailed response! Yes we're in 
>>> INTEL's research programme with NDA so it supposed to be fine. A quick 
>>> sync VC would be great and helpful! Would you be available for it after 
>>> our Friday meeting? 
>>> 
>>> Best Regards,
>>> Ming
>>> -----Original Message-----
>>> From: Frédéric LOUI <> 
>>> Sent: 15. februar 2023 16:30
>>> To: Mingyuan Zang <>
>>> Cc: Henrik Wessing <>; ; 
>>> David Franco <>
>>> Subject: Re: RARE CPE code compilation on Tofino
>>> 
>>> + adding rare-users as your question might interest others
>>> 
>>> Hi,
>>> 
>>> It depends on what you seek to achieve here.
>>> 
>>> 1- If it is to have student use RARE/freeRtr on Wedge, please just use 
>>> RARE/freeRtr ONIE image here:
>>> http://docs.freertr.org/guides/installation/wedge100bf32/onie-nos-install/
>>> 
>>> This will let you install RARE/freeRtr on Debian. If you have some 
>>> difficulties, David recently succeeded in installing RARE/freeRtr on 
>>> their Wedge.
>>> Therefore he can assist/help you in the frame of GP4L context.
>>> 
>>> 2- If you want student to learn how to compile P4 program with INTEL SDE, 
>>> just use bf_switch virtual model on any Linux.
>>> (Preferably Debian stable) But then this part is less documented because 
>>> after that you’d need to run by hand the interface between the control 
>>> plane (freeRtr) and the dataplane (bf_switchd)
>>> 
>>> 3- It also assumes that your students or their supervisors (you) have 
>>> signed NDA with INTEL and that you are familiar with installing INTEL SDE 
>>> and also load bf_switchd modules. In RARE/freeRtr case, we are using 
>>> bf_kpkt modules.
>>> 
>>> -3- is described and part of INTEL P4 training on INTEL SDE here below: 
>>> https://www.intel.com/content/www/us/en/products/network-io/programmable-ethernet-switch/connectivity-education-hub/academy.html
>>> 
>>> Now coming back to your original question:
>>>> When we try to go through RARE’s data plane functions on Tofino 1 in 
>>>> WEDGE100BF32X (with SDE 9.2.0), we got a compilation error with CPE 
>>>> function enabled saying that the code consumed 13 stages as screenshot 
>>>> below. (We enable the function by defining the CPE profile in 
>>>> bf_router.p4 
>>>> as:https://bitbucket.software.geant.org/projects/RARE/repos/rare/browse/profiles/profile-cpe.p4)
>>>>  Other functions like GGSN also shows the similar warning. We were 
>>>> wondering whether it exceeds the capability of Tofino 1? Do we need to 
>>>> try it on Tofino 2? We found that it would cost 12 stages when other 
>>>> functions like ToR enabled? 
>>> 
>>> 
>>> IIRC, I remember that this problem disappeared when you use more recent 
>>> SDE than SDE 9.2.0. INTEL would recommend in any case when you report 
>>> this type of issue to upgrade to latest INTEL SDE.
>>> 
>>> Now that being said in our case, our Wedge is using SDE LTS flavour and 
>>> the code it tested to work with SDE 9.7.0 LTS (and onward i.e 9.9.x, 
>>> 9.11.x and 9.12.x which is the most recent to date)
>>> 
>>>> https://bitbucket.software.geant.org/projects/RARE/repos/rare/browse/profiles/profile-cpe.p4
>>> 
>>> I’m talking under Alexander Gall/Csaba's control , but this profile is 
>>> the output of a profiler software. During our CI/CD pipeline, this 
>>> profile is compiled and included in our ONIE image in the form of a P4 
>>> Nix package.
>>> 
>>> If you are not sure about what is mentioned above. I propose we have a 
>>> quick sync VC where you can explain what you want to achieve.
>>> I would be then able to provide you advise on how to move forward. 
>>> Because a lot of work have been done and in order to learn p4 programming 
>>> you don’t need a real  Wedge physical hardware and p4 stack installed.
>>> 
>>> All the best,
>>> Frederic
>>> 
>>>> Le 15 févr. 2023 à 16:07, Mingyuan Zang <> a écrit :
>>>> 
>>>> Hi Frederic, 
>>>> 
>>>> Recently we’re preparing for the exercises on the RARE router for 
>>>> students. When we try to go through RARE’s data plane functions on 
>>>> Tofino 1 in WEDGE100BF32X (with SDE 9.2.0), we got a compilation error 
>>>> with CPE function enabled saying that the code consumed 13 stages as 
>>>> screenshot below. (We enable the function by defining the CPE profile in 
>>>> bf_router.p4 
>>>> as:https://bitbucket.software.geant.org/projects/RARE/repos/rare/browse/profiles/profile-cpe.p4)
>>>>  Other functions like GGSN also shows the similar warning. We were 
>>>> wondering whether it exceeds the capability of Tofino 1? Do we need to 
>>>> try it on Tofino 2? We found that it would cost 12 stages when other 
>>>> functions like ToR enabled? 
>>>> 
>>>> Can we ask whether such resource consumption is expected, or is there 
>>>> anything we wrongly configured? Is there any other repository that you 
>>>> would recommend us to check?
>>>> 
>>>> Many thanks for your help!
>>>> 
>>>> <image003.jpg>
>>>> 
>>>> Best Regards,
>>>> Ming
>>> 
>> 
>