RARE user and assistance email list

[Alexander Gall <>]

On Wed, 15 Feb 2023 16:29:37 +0100, Frédéric LOUI <> 
said:


> Now coming back to your original question:
>> When we try to go through RARE’s data plane functions on Tofino 1 in 
>> WEDGE100BF32X (with SDE 9.2.0), we got a compilation error with CPE 
>> function enabled saying that the code consumed 13 stages as screenshot 
>> below. (We enable the function by defining the CPE profile in bf_router.p4 
>> as:https://bitbucket.software.geant.org/projects/RARE/repos/rare/browse/profiles/profile-cpe.p4)
>>  Other functions like GGSN also shows the similar warning. We were 
>> wondering whether it exceeds the capability of Tofino 1? Do we need to try 
>> it on Tofino 2? We found that it would cost 12 stages when other functions 
>> like ToR enabled? 


> IIRC, I remember that this problem disappeared when you use more recent SDE 
> than SDE 9.2.0. INTEL would recommend in any case when you report this type 
> of issue to upgrade to latest INTEL SDE.

To expand on this a bit. We're trying to maximize the tables in each
profile. How much resources are actually used on the ASIC depends
heavily on the version of the P4 compiler (newer versions tend to be
better at that, i.e. allowing larger tables for the same P4
program).

There are verion-specific table sizes in the
profiles/<SDE-version>/tofino (and profiles/<SDE-version>/tofino2 for
Tofino2) directories. So if you use one of those versions, simply add
that directory to the compiler include path with "-I".

The profile-*.p4 files in the top-level profiles directory tend to be
those optimized for the newest SDE by csaba but the RARE Nix-based
packaging is currently fixed at SDE 9.7.2 and hence uses
profiles/9.7.2.

If you use a version for which there are no optimized tables, you can
simply play with the values in the relevant file, i.e. for the CPE
profile

$ grep TABLE_SIZE profiles/profile-cpe.p4 
#define PORT_TABLE_SIZE                        512
#define BUNDLE_TABLE_SIZE                      128
#define VLAN_TABLE_SIZE                        512
#define IPV4_LPM_TABLE_SIZE            217088
#define IPV6_LPM_TABLE_SIZE            54272
#define IPV4_HOST_TABLE_SIZE                   256
#define IPV6_HOST_TABLE_SIZE                   256
#define NEXTHOP_TABLE_SIZE                     512
#define _TABLE_SIZE_P4_

In this case you'd want to lower the values of
IPV{4,6}_LPM_TABLE_SIZE until the compiler can fit the tables into the
available stages.

-- 
Alex