RARE user and assistance email list

["mc36" <>]

-------- Forwarded Message --------
Subject: Re: RARE support
Date: Wed, 6 Jul 2022 12:10:55 +0200
From: mc36 <>
Reply-To: 
To: Fr  d  ric LOUI <>, Raul Lopes 
<>
CC: Tim Chown <>, David Richardson 
<>, Duncan Rand <>

hi,
so tofino, as most of these dc asics, cut-through in ingress, and could be in 
egress....
that is, obviously no buffering at all... all it have is somewhat 20mb of 
packet storage
mostly used when the program asks packet replication to more ports... in the 
rest of the
cases, the chip imposes as minimal delay as it can... dpdk dataplane follows 
the same concept there...
i know that there is other, mostly vendor pushed schools with buffering, but 
recent study
show that this causes more issues than it solves:
- realtime (gaming/traditional, udp based voip) usually goes crazy of the 
jitter
- high speed tcp retransmission logic suffers from the jitter too, usually 
causing unnecessary retransmits, making the issue worse
- so not surprisingly a whole rfc (dctcp) is dedicated to how to use switches 
with buffers
i just leave a link here for further studying: https://www.bufferbloat.net/
br,
cs


On 7/6/22 11:59, Fr  d  ric LOUI wrote:
> As for the buffer we can try to see if we can retrieve this information from 
> the dataplane and make it visible to freeRtr.
> Should not be rocket science, but still needs someone to do it. If you are 
> interested into this problematic you can engage with INTEL with ICRP forum 
> (modulo Tim) :)


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