Subject: Rare project developers
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- From: mc36 <>
- To: , Frédéric LOUI <>
- Subject: Re: [rare-dev] AsterFusion X312P-48Y-T at a first glance
- Date: Thu, 9 Feb 2023 17:03:42 +0100
nicee! can we access somehow the box?
can you give a try to freertr.org/rtr-aarch64.tar p4dpdk.bin or p4emu.bin if
they can run out of the box?
thanks,
cs
On 2/9/23 15:54, Fr d ric LOUI wrote:
Hi all !
We are progressing WRT TOFINO2 and TOFINO+DPU(s) hardware installation.
I just wanted to share with you at a first overview/impression of the hybrid
platform: X312P-48Y-T+DPU(s)
(Based on AsterFusion documentation)
- X312P-48Y-T has 12 x QSFP28 port, 48 x SFP28 ports
- TOFINO T32D (with 2 pipes) is used
- Marvell Octeon DPU is an ARM/CPU board somehow similar to Nvidia Bluefield
2 DPU and dpdk driver is rte_pmd_octeontx2
- These DPU(s) are wired internally and have a TOFINO DEV_PORT ID
- DPU(s) can be SSH ed once you are logged into Main Board CPU OS. (i.e
Debian)
- All of our work related to RARE ONIE image is applicable and ONIE id are:
onie_machine: asterfusion_x312p
onie_platform: x86_64-asterfusion_x312p-r0
Therefore RARE/freeRtr integration needs some adjustment developments. It is
similar to 3 installations.
1 installation for Main Board CPU(arch=x86), 1 for DPU_1(arch=arm) and
another fir DPU_2 (arch=arm).
All in all this sounds promising as Marvell Octeon is said to be as much as
powerful as FPGA Stratix 10 (which has been recently declared EoL by INTEL
recently :-( )
All the best
Frederic
- [rare-dev] AsterFusion X312P-48Y-T at a first glance, Frédéric LOUI, 02/09/2023
- Re: [rare-dev] AsterFusion X312P-48Y-T at a first glance, mc36, 02/09/2023
- Re: [rare-dev] AsterFusion X312P-48Y-T at a first glance, Frédéric LOUI, 02/09/2023
- Re: [rare-dev] AsterFusion X312P-48Y-T at a first glance, mc36, 02/09/2023
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